System on a chip (SOC) integrated circuits include assorted subsystems. For example, a smart phone SOC may integrate a modem, a graphics processor, Bluetooth, WiFi, and other subsystems. Each of these subsystems will typically have different timing with regard to entering sleep mode, active mode, or shutdown during operation of the SOC. To enable the subsystems to operate independently with regard to these various modes of operation, it is conventional to power gate the subsystems. If a subsystem is to be powered down, it may then be isolated from a common power rail for the remaining subsystems.
SOCs will typically have two power rails: a memory power rail and also a core logic power rail. The memory power rail provides the power supply voltage to the various embedded memories for the subsystems. In contrast, the core logic power rail provides the power supply voltage to the logic gates. In general, the voltage levels required by embedded memories are different from those required by the core logic for the subsystems. In that regard, it is conventional for both embedded memories and the core logic in the subsystems to be able to shift into a sleep mode, which may also be designated as a retention mode. But embedded memories require a higher power supply voltage to retain their stored values as compared to the reduced power supply voltage that may be used to power logic gates in a sleep mode. If a common power rail were used for both the embedded memories and the core logic, the core logic would waste power during the sleep mode from, for example, unnecessary leakage current loss due to the elevated power supply voltage that would be required to maintain the stored states in the embedded memories. Having independent memory and core logic power rails thus saves power.
Although independent memory and core logic power rails allow the various mode voltages to be optimized for memory and logic operation, power gets wasted from the asynchronous nature of the operating modes for the various subsystems. For example, a WiFi subsystem may need to wake up approximately every 100 ms to check for any incoming messages. The memory power rail and the core logic power rail will then need to be powered so that the WiFI subsystem may wake up accordingly. But these power rails couple to clock trees and other structures in the powered-down subsystems that then lose power through leakage currents.
Accordingly, there is a need in the art for improved power architectures for integrated circuits including a processor subsystem and other subsystems that must interface with the processor subsystem such as through messaging.